The fundamental operating principle of a double buffered data memory in a TDM switch that supports multi-rate input and output with programmable fractional delay, both of which are programmable on a per-stream basis, is that an entire frame of data is stored in one buffer, while an entire frame of data is played out from the other buffer. At the frame boundary, the buffers are logically switched, using hardware multiplexers on the address, data and control signals to the memories, and then the whole cycle repeats for subsequent frames. The switch described in U.S. Pat. No. 6,507,579, the contents of which are herein incorporated by reference, entitled Digital Switch with Rate Conversion works in this way. This switch is named PASIC, and will be subsequently referenced as such. A double buffered technique using a smaller memory is also described in reference U.S. Pat. No. 5,649,148 entitled Fast digital signal processor interface using data interchanging between two memory banks, the contents of which are herein incorporated by reference.
In the most ideal case, any data received during any particular frame can be switched, and appear on the output during the following frame. However, some of the switched data does not appear on the outputs until the duration of the second following frame for two reasons:                1. Data arriving at the very end of a frame cannot be read from its input shift register and loaded into the input memory buffer until after the start of the following frame.        2. Data being switched into timeslots at the very start of a frame must usually be loaded into their respective output shift registers before the start of the frame. For these reasons, some of the switched data is delayed by two frames.        
A TDM switch that supports a constant delay feature will contain some kind of memory buffer used to store any data that would otherwise appear on the outputs in one frame and to delay that data by one frame. In this manner, all data received on any particular frame would then appear on the second frame following that on which it was received. Other ways of implementing a constant delay feature are possible. Examples of commercially available TDM switches that support this constant delay feature are Mitel MT8985 and MT8986 devices described in Mitel Semiconductor Digital Switching and Networking Components; Issue 11, 1997.
In the prior art, if there are multi-rate streams together with fractional delay, and these features are controllable on a per-stream basis, then the duration of the channel times will vary depending on the data rate and fractional delay setting, and so, therefore, the point in time that the data can be presented to the data memory buffer also varies. Because the data streams can have different rates or fractional delays programmed, there is no single point in time that the memory buffers can be logically switched and be guaranteed to contain one complete frame of data.
In a variable delay throughput TDM switch, it does not matter how many frames the data is delayed, so there is no problem. However, most modern TDM switches include a constant delay feature which demands that any data received during any particular frame will be available on the outputs during a frame that is a fixed number of frames later, regardless of the programmed connection path, or any other programmed features. Preferably, this number is two frames.
The most significant traditional technique to overcome this problem is to use a second data memory instance. Data memory buffers are switched at a single point in time, usually but not necessarily after the D1 data is received (See FIG. 1). The next frame data is stored in the second different data memory buffer. Each memory buffer may or may not contain exactly one complete frame of data, depending on the programmed data rates per stream.
A hardware unit is then used to appropriately select the data from one of the two data memory instances, depending on the connection path. The obvious disadvantage of this is the size of the extra memory instance. Also, this technique usually incurs an additional frame delay in the output.
Many lower bandwidth TDM switches do not use a double buffered data memory as described, but rather, they use multiple data memory instances, usually two or three, and a hardware switching unit that has sufficient time and performance to both store the input data, and read out the desired connection data for loading into the output serial shift registers in sequence.
While this technique may be advantageous from a hardware standpoint, in very large switches, for example, having 32,768 channels, this particular switching technique cannot be used because there is not enough time to execute both a data store sequence into the data memory, and a data recovery and switching sequence in the available time. The double buffered technique, as used in the PASIC significantly improves the through-put capability by logically separating the data storage portion of the switch from the data recall portion.
A third technique is to provide many smaller double buffered data memory segments, one each for each input stream, and then to appropriately switch each one at the point in time when they have collected exactly one frame of data. This technique works well, but incurs the disadvantage of having many small memory elements. Most SRAM implementations are less efficient at smaller sizes.